fix: Align CRC calculation with ETSI EN 300 706 standard
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This commit is contained in:
2026-02-07 14:27:37 +01:00
parent de296b4711
commit 9b846970b8

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@@ -78,11 +78,12 @@ class Page:
def calculate_crc(self) -> int: def calculate_crc(self) -> int:
""" """
Calculates the CRC-16 (CCITT) checksum for the page. Calculates the CRC-16 (CCITT) checksum for the page.
Covers Rows 0 to 23. According to ETSI EN 300 706 (Section 9.4.1.2 & Figure 13):
Row 0: Skips first 8 bytes (Header/Control). Uses bytes 8-39. - Covers Row 0 columns 8-31 (Bytes 14-37 in packet, excluding header and clock).
Rows 1-23: Uses all 40 bytes. - Covers Rows 1-25 columns 0-39 (Bytes 6-45 in packet).
Data is 7-bit (stripped parity). - Total 1024 bytes (8192 bits).
Initial value: 0 (ETSI EN 300 706 9.4.1.2). - Data is 7-bit (stripped parity).
- Initial value: 0.
""" """
crc = 0 crc = 0
poly = 0x1021 poly = 0x1021
@@ -104,18 +105,27 @@ class Page:
for p in self.packets: for p in self.packets:
rows[p.row] = p rows[p.row] = p
for r in range(24): # 0 to 23 for r in range(26): # 0 to 25
# Determine column range
if r == 0:
start_col, end_col = 8, 32 # Cols 8-31 (24 bytes)
else:
start_col, end_col = 0, 40 # Cols 0-39 (40 bytes)
if r in rows: if r in rows:
data = rows[r].data data = rows[r].data
start_col = 8 if r == 0 else 0 # Ensure data is long enough (should be 40)
d_len = len(data)
for i in range(start_col, 40): for i in range(start_col, end_col):
byte_val = data[i] & 0x7F # Strip parity if i < d_len:
byte_val = data[i] & 0x7F # Strip parity
else:
byte_val = 0x20 # Pad with space if short
crc = update_crc(crc, byte_val) crc = update_crc(crc, byte_val)
else: else:
# Missing row? Usually treated as spaces (0x20) # Missing row treated as spaces
start_col = 8 if r == 0 else 0 for i in range(start_col, end_col):
for i in range(start_col, 40):
crc = update_crc(crc, 0x20) crc = update_crc(crc, 0x20)
return crc return crc